The 2007 Carnival Procession at Las Palmas de Gran Canaria (Canary Islands, Spain)The 2007 Carnival Drag-Queen of Las Palmas de Gran Canaria (Canary Islands, Spain)

Ph.D. Proposals

Oferta de Proyectos de Tesis Doctoral

(e-mail : dbenitez(at)dis(dot)ulpgc(dot)es)

This Ph.D. project will study the following problem:

– The design of embedded architectures for energy-efficient smart buildings

 

Keywords: System-On-Chip, Smart Buildings, Konnex, Energy Efficiency, Home Systems, Ubiquiotous Computing, Embedded Computer Architectures, SCADA software

 

SystemOnChip-based Architectures for Energy Efficient Buildings

(Arquitecturas basadas en SystemOnChip para Edificios Energéticamente Eficientes)

Proyectos de Tesis Doctoral

 

Reconfigurable On-Chip Caches

 

High-Performance Reconfigurable Computing

The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits diminishing returns, while the higher cache latency hurts performance.

We have design the Amorphous Cache (AC), a reconfigurable L2 on-chip cache aimed at improving performance as well as reducing energy consumption. AC is composed of heterogeneous sub-caches as opposed to common caches using homogenous sub-caches. The sub-caches are turned off depending on the application workload to conserve power and minimize latencies.

A novel reconfiguration algorithm based on Basic Block Vectors has been proposed to recognize program phases, and a learning mechanism is used to select the appropriate cache configuration for each program phase.

We have compared our reconfigurable cache with existing proposals of adaptive and non-adaptive caches. Our results show that the combination of AC and the novel reconfiguration algorithm provides the best power consumption and performance.

Keywords— Cache, Dynamic adaptation, Processor evaluation.

 

This Ph.D. project will study the following problem:

– The design of reconfigurable caches for multi-core processors

 

 

Frequently, automated solutions to Computer Science and Engineering (CSE) problems require that billion to trillion of complex operations to be applied on input data acquired from the real world. In many cases, these solutions must be worked out in a determined time interval. In other cases, the greater the number of operations per time unit, the highest precision the results are obtained in a time interval. Both, availability and precision of information are key elements in resolving human being problems or making common living more comfortable and longer.

 

 

Reconfigurable Computer

Reconfigurable Amorphous Cache

SCADA software

In order to get this performance goal, high-performance computing is a research and development domain in which solutions to a lot of CSE problems are provided by means of a combination of high-performance computers and parallel programs. Some years ago, the fastest computers used to integrate central processing units that were specialized in performing the highest number of operations per second. However, nowadays, high-performance computers are based on a large population of commodity programmable processors, which can be also integrated in desktops or laptops.

High-Performance Customizable Computing (HPCC) is a different way of doing high-performance computing. Instead of having only programmable processors, customizable computers additionally integrate hardware devices that can be customized for a portion of a specific program.

This Ph.D. project will study the following HPCC problems:

– Hardware abstraction and Programming models: Memory model, Communication model, and Parallel Processing (coarse-grain and fine-grain architectures)

– Development tools: explicit and implicit parallelism model

– Heterogeneous architectures: multi-core, GPUs, FPGAs, CPLDs, Extensible Processing Platforms