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Reconfigurable Cache Memories

Reconfigurable Caches for Adaptive High-Performance and Embedded Processors

For some programs, larger monolithic caches are suboptimal and actual software performance is dropping with increasing cache size because processors benefit more from smaller and faster caches. For every processor workload, at some point the increase in cache capacity hits diminishing returns but the higher latency hurts performance.

We have proposed the microarchitecture of two types of reconfigurable caches and evaluated their impacts on processor performance and cache energy consumption.

FPCA is a specialized reconfigurable circuit for the L1 cache memory of a general-purpose processor. In comparison with a conventional cache, the clock speed is only slightly slower. The temporal and power overheads are low because programs exhibit large execution phases and reconfigurations are only sporadically activated. The FPCA cache can be used in designs with different initial budgets for the processor development: from high-performance to embedded processors, each of them can adopt a distinct FPCA. Our adaptive cache can be efficiently exploited not only by the range of applications and execution phases, but also by tuning a preferred metric (performance, power, etc.). We also have proposed an on-line control algorithm called Cache Matching Algorithm for instantaneously tuning the FPCA cache with accuracy, minimal hardware cost, and an overhead that is independent of the number of tuneable cache configurations.

 

The microarchitecture of a processor with adaptive with a Fild-Programmable L1 Cache Array

The Amorphous Cache. A reconfigurable cache for the L2 cache memory

Papers:

D. Benitez, J.C. Moure, D.I. Rexachs, E. Luque; A Reconfigurable Cache Memory with Heterogeneous Banks; Proceedings of the Design, Automation & Test in Europe 2010 (DATE2010, Reconfigurable Architectures session); pp. ?. ACM, 2010.

D. Benitez, J.C. Moure, D.I. Rexachs, E. Luque; Evaluation of the Field-Programmable Cache: Performance and Energy Consumption; Proceedings of the Conference on Computing Frontiers (CF06); Sheridan Printing Company, Inc., 2006

D. Benitez, J.C. Moure, D.I. Rexachs, E. Luque; A Reconfigurable Data Cache for Adaptive Processors; Intl. Workshop on Applied Reconfigurable Computing (ARC2006), Lecture Notes in Computer Science, 2006

D. Benitez, J.C. Moure, D.I. Rexachs, E. Luque; Performance and Power Evaluation of an Intelligently Adaptive Data Cache; 12th Annual IEEE International Conference on High Performance Computing (HiPC 2005), Lecture Notes in Computer Science Vol. 3769, pp. 363-375, 2005

We have also proposed the Amorphous Cache, a novel mechanism for dynamically reconfigurable large on-chip caches that provides different cache configurations in terms of size and set associativity. The cache configurations vary in both power consumption and access latency. The mechanism decreases power consumption and improves performance by disabling heterogeneous sub-caches in all phases of an program that do not benefit from larger or highly associative caches. Power can be saved because the sub-caches are disconnected from the power supply, and performance can improve because the smaller caches have lower access latencies without significantly increasing the miss rate.

We also propose a dynamic reconfiguration technique called BBV&NDP, which chooses the best cache configuration using a Basic Block Vector based mechanism.